000			00621nam a22001697a 4500
003			inkolt
005			20240926145218.0
008			240712s2024 ii ||||| |||| 00| 0 eng d
082			_a621.31 _bTHA
100			_aThamerci, Rajendra _912548
245			_aComprehensive design and verification of spi, spi memory, and ethernet communication protocols using system verilog and uvm / _cRajendra Thamerci.
260			_aHamirpur : _bNational Institute of Technology, _c2024
300			_ax, 49p.
502			_bMaster of Technology _cEE-NITH _d2024
720			_aKhanna, Gargi _eGuide / Supervisor
942			_cTD _n0 _xRajesh Pal Patial _y6 _z Rajesh Pal Patial
999			_c6054 _d6054