| 000 | 00540nam a22001697a 4500 | ||
|---|---|---|---|
| 003 | inkolt | ||
| 005 | 20240507102600.0 | ||
| 008 | 230726s2023 ii ||||| |||| 00| 0 eng d | ||
| 082 |
_a621.38 _bBHA |
||
| 100 | 1 |
_aBharti, Varun _912038 |
|
| 245 | 1 | _aDesign and analysis of logic gates using step channel tfet | |
| 260 |
_aHamirpur : _bNational Institute of Technology, _c2023. |
||
| 300 | _axv, 71p. | ||
| 502 |
_bDual Degree Program _cEC-NITH _d2023 |
||
| 720 |
_aYadav, Dharmendra Singh _eGuide / Supervisor |
||
| 942 |
_cTD _n0 _xRajesh Pal Patial _y6 _z Rajesh Pal Patial |
||
| 999 |
_c5559 _d5559 |
||