Design and performance evaluation of low power optimized VLSI adder circuits.
By: Puri, Rakhi
Material type: TextPublisher: Hamirpur : National Institute of Technology, 2008Description: xvii, 75pGenre/Form: Thesis or Dissertation DDC classification: 621.38 Dissertation note: Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2008 Guide / Supervisor: Chandel, Rajeevan.Item type | Current location | Call number | Status | Date due | Barcode |
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Thesis or Dissertation | Electronics and Communication Engineering (Departmental Library) On Display | 621.38 PUR (Browse shelf) | Available | EC-DR-01 |
Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2008
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