Design of a true-single -phase-clocked dual-edge-triggered flip-flop for low power applications
By: Jaswal, Ishani
Material type: TextPublisher: Hamirpur : National Institute of Technology, 2022Description: viii, 63pDDC classification: 621.38 Dissertation note: Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2022 Guide / Supervisor: Khanna, GargiItem type | Current location | Call number | Status | Date due | Barcode |
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Thesis or Dissertation | Central Library On Display | 621.38 JAS (Browse shelf) | Available | TH-1516 | |
Thesis or Dissertation | Electronics and Communication Engineering (Departmental Library) On Display | 621.38 JAS (Browse shelf) | Available | EC-DR-367 |
Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2022
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