Performance analysis of full adder and subtractor using hybrid cmos memristor and adiabatic logic / Kush Thakur.
By: Thakur, Kush
Material type:
TextPublisher: Hamirpur : National Institute of Technology, 2024Description: xi, 61pDDC classification: 621.38 Dissertation note: Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2024 Guide / Supervisor: Rana, Ashwani Kumar
| Item type | Current location | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|
Thesis or Dissertation
|
Central Library On Display | 621.38 THA (Browse shelf) | Available | TH-2242 |
Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2024
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