Thamerci, Rajendra <br/><br/>
Comprehensive design and verification of spi, spi memory, and ethernet communication protocols using system verilog and uvm / 
Rajendra Thamerci. 
 - Hamirpur :  National Institute of Technology,  2024 
 - x, 49p. 
<br/><br/>
<br/><br/><label>Dewey Class. No.: </label>621.31  / THA