Comprehensive design and verification of spi, spi memory, and ethernet communication protocols using system verilog and uvm / Rajendra Thamerci.
By: Thamerci, Rajendra
Material type:
TextPublisher: Hamirpur : National Institute of Technology, 2024Description: x, 49pDDC classification: 621.31 Dissertation note: Master of Technology, Department of Electrical Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2024 Guide / Supervisor: Khanna, Gargi
| Item type | Current location | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|
Thesis or Dissertation
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Central Library | 621.31 THA (Browse shelf) | Available | TH-2500 |
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Master of Technology, Department of Electrical Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2024
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