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Differential power analysis resistant secured s-box circuit using cmos transmission gate logic / Praksham Mahajan.

By: Mahajan, Paksham

Material type: Text

TextPublisher: Hamirpur : National Institute of Technology, 2024Description: xiv, 73pDDC classification: 621.38 Dissertation note: Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2024 Guide / Supervisor: Chandel, Rajeevan

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Item type	Current location	Call number	Status	Date due	Barcode
Thesis or Dissertation	Central Library On Display	621.38 MAH (Browse shelf)	Available		TH-2233

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Previous	621.38 LIG Reduction of short channel effects in bulk planar junctionless transistor	621.38 LOM Design and implementation of 1 bit full adder using 45nm cmos technology	621.38 MAH Implementation of logic gates using charge plasma tfet	621.38 MAH Differential power analysis resistant secured s-box circuit using cmos transmission gate logic /	621.38 MAK An energy efficient wsns protocol for the avalanche prediction in himalayan region	621.38 MAL Design and development of planar dipole antenna for terahertz application	621.38 MAN Performance analysis of double gate junctionless transistor	Next

Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2024

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Differential power analysis resistant secured s-box circuit using cmos transmission gate logic / Praksham Mahajan.

By: Mahajan, Paksham

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