Design and analysis of logic gates using step channel tfet
By: Bharti, Varun
Material type:
TextPublisher: Hamirpur : National Institute of Technology, 2023Description: xv, 71pDDC classification: 621.38 Dissertation note: Dual Degree Program, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2023 Guide / Supervisor: Yadav, Dharmendra Singh
| Item type | Current location | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|
Thesis or Dissertation
|
Central Library On Display | 621.38 BHA (Browse shelf) | Available | TH-1817 |
Dual Degree Program, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2023
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