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Design and implementation of 1 bit full adder using 45nm cmos technology

By: Lomash, Shatakshi

Material type: Text

TextPublisher: Hamirpur : National Institute of Technology, 2022Description: viii, 30pDDC classification: 621.38 Dissertation note: Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2022 Guide / Supervisor: Rana, Ashwani Kumar

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Item type	Current location	Call number	Status	Date due	Barcode
Thesis or Dissertation	Central Library On Display	621.38 LOM (Browse shelf)	Available		TH-1527
Thesis or Dissertation	Electronics and Communication Engineering (Departmental Library) On Display	621.38 LOM (Browse shelf)	Available		EC-DR-411

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Previous	621.38 KUS Two - bit branch prediction and branch target buffer in the risc-v instance: design and evaluation	621.38 LAL A novel design and analysis of binary comparator using quantum-dot cellular automata (qca)	621.38 LAT An improved comb structured battery-less intraocular pressure sensor for glaucoma diagnosis	621.38 LOM Design and implementation of 1 bit full adder using 45nm cmos technology	621.38 MAD Implementation of a self motivated arbitration scheme for the multilayer AHB busmatrix.	621.38 MAK An energy efficient WSNs protocol for the avalanche prediction in Himalayan region.	621.38 MAN Performance analysis of double gate junctionless transistor	Next

Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2022

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Design and implementation of 1 bit full adder using 45nm cmos technology

By: Lomash, Shatakshi

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