Performance analysis of low power sram cells designed using cmos and cntfet technologies
By: Yadav, Nivali
Material type:![Text](/opac-tmpl/lib/famfamfam/BK.png)
Item type | Current location | Call number | Status | Date due | Barcode |
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Central Library On Display | 621.38 YAD (Browse shelf) | Available | TH-1528 | |
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Electronics and Communication Engineering (Departmental Library) On Display | 621.38 YAD (Browse shelf) | Available | EC-DR-366 |
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Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2022
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