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Investigation of fully depleted soi mosfet for low power digital circuits

By: Satyanarayana, B

Material type: Text

TextPublisher: Hamirpur : National Institute of Technology, 2017Description: x, 53pGenre/Form: Thesis or Dissertation DDC classification: 621.38 Dissertation note: Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2017 Guide / Supervisor: Sharma, Vinod Kumar

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Item type	Current location	Call number	Status	Date due	Barcode
Thesis or Dissertation	Central Library On Display	621.38 SAT (Browse shelf)	Available		TH-478
Thesis or Dissertation	Electronics and Communication Engineering (Departmental Library) On Display	621.38 SAT (Browse shelf)	Available		EC-DR-289

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Previous	621.38 SAI Design and analysis of finfet structure.	621.38 SAK Modeling and simulation of ingan based quantum well light emitting diode	621.38 SAL D flip-flop design using pass transistors and its application to multi bit flip-flops	621.38 SAT Investigation of fully depleted soi mosfet for low power digital circuits	621.38 SET Design and analysis of image compression algorithm using wavelet transform.	621.38 SET Design and Analysis of Image Compression Algorithm using Wavelet Transform	621.38 SHA Design and analysis of low phase noise CMOS pll frequency synthesizer.	Next

Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2017

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Investigation of fully depleted soi mosfet for low power digital circuits

By: Satyanarayana, B

Browsing Electronics and Communication Engineering (Departmental Library) shelves, Shelving location: On Display Close shelf browser