Design and performance analysis of CMOS SRAM cells in 32nm technology node.
By: Rathour, Ravi
Material type:![Text](/opac-tmpl/lib/famfamfam/BK.png)
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Electronics and Communication Engineering (Departmental Library) On Display | 621.38 RAT (Browse shelf) | Available | EC-DR-235 |
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Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2015
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