Power, delay and area efficient asynchronous logic design.

By: Kumar, Gautam
Material type: TextTextPublisher: Hamirpur : National Institute of Technology, 2013Description: xiv, 96pGenre/Form: Thesis or Dissertation DDC classification: 621.38 Dissertation note: Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2013 Guide / Supervisor: Chandel, Rajeevan.
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Thesis or Dissertation Thesis or Dissertation Electronics and Communication Engineering (Departmental Library)
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621.38 KUM (Browse shelf) Available EC-DR-146

Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2013

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