Design and validation of phase lock loop.
By: Veeresh, V
Material type: TextPublisher: Hamirpur : National Institute of Technology, 2009Description: xiii, 85pGenre/Form: Thesis or Dissertation DDC classification: 621.38 Dissertation note: Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2009 Guide / Supervisor: Kumar, Gagnesh.Sharma, Manish.Item type | Current location | Call number | Status | Date due | Barcode |
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Thesis or Dissertation | Electronics and Communication Engineering (Departmental Library) On Display | 621.38 VEE (Browse shelf) | Available | EC-DR-18 |
Master of Technology, Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Himachal Pradesh, India - 177005. 2009
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